1. Field of the Invention
This invention relates to software programs and related hardware for electronic design automation (EDA), and in particular to such EDA "tools" for emulating logic circuits.
2. Description of the Background Art
Various EDA tools are known for designing integrated circuits. In a typical EDA tool suite, Computer Aided Engineering and Design (CAE/CAD) software are configured in various engineering workstations to provide design engineers with automated or semi-automated tools for defining and verifying circuits, typically either in the form of discrete integrated circuits (chips) or subsystem printed circuit boards.
Circuit definition is generally accomplished with schematic-capture tools, which allow the designer to enter symbolic representations of components and interconnections for a particular circuit. More recently, circuit definition has also been accomplished with synthesis tools, which allow the designer to describe textually the function of a particular circuit design through various hardware description languages (HDL).
After a particular circuit is defined, the design engineer then verifies the accuracy of the circuit. The circuit verification step is typically accomplished through simulation, which serves to test the correctness of the circuit's functional behavior in response to various applied stimuli, such as digital input signals or test vector patterns. Thus, if the design engineer determines during simulation that the circuit design is defined incorrectly, then the circuit may be re-defined, typically through iterative modifications of either the circuit schematic or the HDL file.
Typically, once the circuit definition and verification steps are completed, the CAE tool portion of the EDA tool suite then generates a circuit description file, or "netlist." The netlist contains a description of the circuit's components and electrical interconnections, and this file is used by the CAD tool portion of the EDA tool suite for performing automatic chip or board-level lay-out. Lay-out information is then converted by the CAD tool into a physical description or pattern generation file, typically referred to as a "PG tape," which is used for photomask manufacturing.
The chip manufacturing process is initiated essentially at the photomask manufacturing step since the circuit design is verified and committed by the design engineer at that time to proceed to wafer fabrication, where silicon chips embodying the verified circuit are made. The manufacturing process includes semiconductor wafer processing, device assembly and testing, and thus can be expensive and time-consuming. An analogous process flow is followed conventionally for circuit-board manufacturing.
If the manufactured prototype chip or board (containing chips) is somehow non-functional and requires redesign, then additional cost and delay are incurred. Thus, it is desirable to ensure that the netlist file, which is used to manufacture a particular circuit, correctly represents the circuit design intended by the design engineer.
Despite the circuit verification or simulation steps typically employed to test for circuit correctness, however, the prototype circuit may nonetheless be non-functional because of various failure modes, such as incorrect simulation modeling, inadequate simulation vector testing and improper system interfacing.
Thus, to verify further the correctness of the circuit netlist file (i.e., prior to committing the circuit design to manufacturing,) an approach known as circuit emulation is sometimes used in conjunction with existing EDA tools. Emulation aims to reduce or eliminate delays and costs associated with re-designing and re-manufacturing non-functional circuit prototypes.
In general, emulators function similarly to simulators in that both emulator and simulator tools imitate the functional behavior of a designed circuit, typically for test or debug purposes. However, in comparison to simulators, which merely apply user-specified input test vector patterns as stimuli to simulation models of a given circuit, emulators actually interface a functional, emulated circuit to its intended target system. In this way, the emulated circuit is electrically coupled within its design environment, thereby enabling real-time validation of the circuit under actual operating conditions, where the stimuli applied to the prototype circuit may be substantially more comprehensive. Thus, emulators are designed to verify the functional correctness of circuits more accurately by avoiding failure modes associated with inadequate simulation vector testing and improper system interfacing of prototype circuit designs.
In addition, since emulators are configured to provide an actual implementation to represent functionally a given emulated circuit design (i.e., through either conventional "bread-boarded" discrete logic or various reconfigurable logic devices, onto which the netlists of circuit designs are down-loaded,) then failure modes associated with incorrect simulation modeling are largely eliminated.
Presently, emulation tools operate in conjunction with conventional EDA tools to enable automatic down-loading of netlists to various reconfigurable logic devices, such as field programmable gate arrays (FPGAs). This general EDA approach of combining reconfigurable logic devices with emulation technology is particularly appealing since it facilitates iterative testing and debugging of circuit designs, without the inconvenience and complexity of rewiring bread-boards.
As circuit designs grow in functional complexity and gate count, however, the usefulness of known EDA tools employing reconfigurable emulation techniques becomes more limited. For instance, with larger circuits, EDA CAD tools increasingly encounter routing congestion, typically due to larger netlists requiring multiple re-compilations in order to achieve routing of all signal subnets. Also, even when larger circuits are eventually implemented for emulation (i.e., on breadboards or FPGAs,) it may still be difficult or impossible to access various internal nodes or states within the emulated circuits for test or debug purposes.
Therefore, it would be desirable to provide EDA tools, which use reconfigurable logic devices in emulation applications, whereupon the foregoing type of congestion-related limitations are avoided, such that prototype circuit debugging is thereby facilitated.